The proposed testing method is e ecti ve i n reducing testing time when ov erhead time for reference voltage presetting in test mode, e.g. when measuring SAR ADC o set and gain, is comparativ ely small 9. (ii) For high-speed sampling SAR ADCs, the proposed method cannot take care of the D A C output incomplete set- tling problem in earlier stages 36; ho wever in such cases, the SAR ADC can be tested in normal mode (not using the proposed method) because high-speed sampling ADC linearity testing time is relativ ely short. (iii) The DC linearity testing time of an n -bit ADC with sam- pling frequency of f s is giv en as follows (T able 1): (16 64) 2 n f s W e assume here that a testing time of 1 sec.Learn more DOI: 10.1587transele.E94.C.1061 Source: DBLP Cite this publication Tomohiko Ogawa Haruo Kobayashi 30.23 Gunma University 4 Satoshi Uemori Yohei Tan Show more authors Hide Abstract Design for Testability That Reduces Linearity Testing Time of SAR ADCs Discover the worlds research 17 million members 135 million publications 700k research projects Join for free Figures - uploaded by Kiichi Niitsu Author content All content in this area was uploaded by Kiichi Niitsu Content may be subject to copyright.Typical ADC testing time with ATE.Our SAR ADC chip performance.
Advertisement Content uploaded by Kiichi Niitsu Author content All content in this area was uploaded by Kiichi Niitsu on Jan 03, 2015 Content may be subject to copyright. Y AMA GUCHI, Nonmember, and Kiichi NIITSU, Member SUMMAR Y This brief paper describes design-for -testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. W e present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its e ectiv eness. Introduction Successi ve Approximation Re gister (SAR) ADCs are no w widely used in applications such as automotive electron- ics, f actory automation, and pen digitizer applications that require low cost, lo w po wer, medium speed, high ac- curacy and high reliability 16. Such ADCs need to be production-tested using automatic test equipment (A TE); testing of DC linearity is very important, but testing of high- resolution low-sampling-rate SAR ADCs takes considerable time. This brief paper describes design-for -testability (DFT) circuitry that enables DC linearity testing time to be re- duced. W e ha ve implemented the proposed DFT circuitry in an SAR ADC, and our chip measurement results v alidate the concept; the DFT circuit o verhead is small, so it is prac- ticable. Dft 55Mm Generator And SARProposed DFT for SAR ADC Linearity An SAR ADC consists of a sample and hold circuit, a com- parator, a DA C, a timing generator and SAR logic circuit, and operates based on the principle of a balance (Fig. When testing high-resolution ADCs, DC linearity is one of the most important test items, and any method of reducing testing time while maintaining test accurac y can reduce test- ing cost 7, 8. When testing the SAR ADC, we know (that is, we can control) the analog input v alue a t each sampling time, so we can reduce the number of SAR conv ersion steps (and hence the SAR ADC DC linearity testing time) by preadjusting the reference voltages accordingly. W e here describe cir- cuitry that can be built into the SAR ADC to enable such Manuscript recei ved October 4, 2010. The authors are with the Department of Electronic Engineer- ing, Graduate School of Engineer ing, Gunma Univ ersity, Kiryu- shi, 376-8515 Japan. As shown in Fig. 2, the reference voltage lev els that correspond to testing-time D A C inputs are stored in the RAM (or ROM) of our SAR ADC. For DC linearity test- ing, suppose that the SAR ADC is supplied with a staircase ramp input with very slo w slope so that the value of the ramp input is controlled (known) at each sampling time, and sup- pose that the SAR ADC (5-bit, 5-step in this example) w ould normally use a 4-step binary search algorithm during test- ing to c onrm that linearity is acceptable. Since we know the input v alue at each test point, if we preadjust the corre- sponding comparator reference voltages to values close to the input voltages, then we do not need a 4-step algorithm; fewer steps (say, 2 steps) will be su cient, as illustrated in Fig. A TE can play the role of the digital controller, and the design may share the test mode RAM with the normal mode RAM. The o verhead chip area for the DFT was less than 3 in our SAR ADC design.) Fig. W e note that testing and measurement are similar but di erent technologies. When measuring, the analog input value is uncontrollable and unkno wn. For an actual 10-bit binary s earch SAR ADC whose Fig. Operation of the proposed built-in circuitry in Fig. Normal mode. ( b) T est mode. Content Ti m e 1) Setup time for mod- ule less than 1 msec 2) Settling time for mod- ule and DUT sev eral msec 3) DC linearity testing time 2 bit (16 64) (ADC con ver - sion time) 4) SINAD testing time 2 bit (1 4) (ADC conv er- sion time) 5) Time for data transfer and operation sev eral msec 6) Other test time sev eral msec INL may be expected to be within 8 LSBs, we found that the number of SAR ADC steps required at each test volt- age could be reduced from 10 to 4. In our experience with an A TE, the ratios of the DC linearity testing time, SIN AD testing time and ADC set up data transfer time may be 88: 9: 3 in case of a 10 bit 100 kS s SAR ADC (T able 1) 9. Hence we can reduce testing time by approximately half us- ing the above testing methodology. Resolution 10 bit ENOB 9.5 bit Sampling Speed upto 3 MHz Supply V oltage 1.5 V Power Consumption 5. W 3M S s T echnology 180 nm CM OS Fig. Photo of chip (2.5 mm 2.5 mm) with two SAR ADCs. Chip Implementation and Measurement Results So far we have done a brief v alidation of this methodol- ogy using a chip implementation of our SAR ADC that in- cludes the additional testing-specic circuitry. Its perfor- mance summary is shown in T able 2, and its chip photo is shown in Fig. Our measurement results in Fig. ADC output after 4 steps in testing mode is compa- rable to that after 10 steps of normal binary operation, which seems to validate the basic concepts of this testing method- ology; the data in Figs. Discussion (i) The higher the resolution and the slower the sampling rate of an SAR ADC, the longer its linearity testing takes. The proposed testing method is e ecti ve i n reducing testing time when ov erhead time for reference voltage presetting in test mode, e.g. SAR ADC o set and gain, is comparativ ely small 9. For high-speed sampling SAR ADCs, the proposed method cannot take care of the D A C output incomplete set- tling problem in earlier stages 36; ho wever in such cases, the SAR ADC can be tested in normal mode (not using the proposed method) because high-speed sampling ADC linearity testing time is relativ ely short. The DC linearity testing time of an n -bit ADC with sam- pling frequency of f s is giv en as follows (T able 1): (16 64) 2 n f s W e assume here that a testing time of 1 sec.
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